It is known to provide a cascade of a boost converter for PFC followed by a PWM (pulse width modulation) buck converter for producing a lower voltage than the typically high output voltage of the PFC converter, and to operate these in a synchronized manner using a single clock reference. Such cascaded converters are described for example in Hwang U.S. Pat. No. 5,565,761, issued Oct. 15, 1996 and entitled “Synchronous Switching Cascade Connected Off-Line PFC-PWM Combination Power Converter Controller”, and Hwang et al. U.S. Pat. No. 5,798,635, issued Aug. 25, 1998 and entitled “One Pin Error Amplifier And Switched Soft-Start For An Eight Pin PFC-PWM Combination Integrated Circuit Converter Controller”.
Another arrangement comprising cascaded PFC and PWM power converters is known from Fairchild Semiconductor Application Note 42047 entitled “Power Factor Correction (PFC) Basics”, Rev. 0.9.0, Aug. 19, 2004. Various PFC arrangements and their control are known for example from Chapter 1, entitled “Overview of Power Factor Correction Approaches”, of “Power Factor Correction (PFC) Handbook”, ON Semiconductor document HBD853/D, Rev. 2, August 2004.
In the Fairchild and ON Semiconductor documents referred to above, a PFC control unit is supplied with signals representing the input voltage, input current, and output voltage of the PFC converter and produces a PWM control signal using average current mode control to provide the PFC converter with a substantially resistive input.
In “The Dynamics of a PWM Boost Converter with Resistive Input” by S. Ben-Yaakov et al., IEEE Transactions on Industrial Electronics, Vol. 46, No. 3, June 1999, pp. 613-619 there is described an indirect PFC converter control scheme in which output voltage and input current, but not input voltage, of a boost converter operating in CCM are sensed to control the off-time duty cycle Doff of the converter to provide an equivalent resistive input, i.e. a power factor of 1. In this control scheme, operating in accordance with an equation Vin(av)=Doff.Vo(av) where Vin(av) is the average input voltage and Vo(av) is the average output voltage, an output voltage error is multiplied by average input current to produce a voltage that is modulated by a PWM modulator to produce Doff. This indirect control method has advantages such as being less susceptible to switching noise which is normally present on the input rectified line voltage, and not needing to monitor this voltage directly.
For relatively high converter powers, for example of about 200 W or more, it is desirable to operate the PFC converter in continuous current mode (CCM), in which a primary switch of the PFC converter is turned on before an inductor current has fallen to zero, to provide advantages such as relatively smaller inductor current swings and peak current. A PFC power converter operated in CCM usually has a fixed switching frequency. The PFC-PWM cascaded converters referred to above use an oscillator that determines the switching frequency for both converters.
Ta-yung Yang U.S. Pat. No. 6,903,536, issued Jun. 7, 2005 and entitled “PFC-PWM Controller Having Interleaved Switching”, discloses another cascade of PFC and PWM converters, with interleaved switching and an oscillator determining the switching frequency of both converters. In this arrangement, the switching frequency is decreased under light-load and zero-load conditions, so that power consumption of the power converter is reduced under such conditions.
Typically, a lower power PFC converter is operated in critical conduction mode, also referred to as transition mode, in which the primary switch of the converter is turned on just at the time that the inductor current has fallen to zero. In this case the switching frequency is variable because it is determined by the operating conditions of the converter rather than by an oscillator. This is a discontinuous conduction mode (DCM) in which the inductor current falls to zero.
Another operating mode, referred to as fixed off-time (FOT) control and known from STMicroelectronics Application Note AN1792, “Design Of Fixed-Off-Time-Controlled PFC Pre-Regulators With The L6562”, November 2003, uses a switching waveform with a fixed off-time and hence a variable frequency, without an oscillator. In this mode DCM and CCM operation occur alternately at different phases during a cycle of an input rectified AC line voltage. This mode requires the switching frequency to be very limited to keep distortion within acceptable limits, unless the off-time is made a function of the instantaneous line voltage, with more complexity and less predictable results.
It is desirable for the converter switching frequency to be relatively high, in order to reduce the sizes of reactive components. However, switching losses increase with increasing switching frequency, resulting in practical upper limits to the switching frequencies that can be used.
It is also known to reduce power converter switching losses by using a resonant mode power converter, taking advantage of zero voltage switching (ZVS) and/or zero current switching (ZCS). Examples of resonant mode converters include series resonant, parallel resonant, series parallel resonant or LCC, and LLC converters which are preferred. An LLC converter is operated with a variable frequency switching waveform, which is a substantially square waveform with dead times to avoid simultaneous conduction of the half bridge switches. A higher frequency corresponds to a lighter load, which is the converse of the PFC-PWM converter arrangement of Ta-yung Yang referred to above. Although a particular LLC converter may be designed for operation over a relatively narrow range of frequencies, different LLC converters for use in different applications, and with potentially different input voltages, may be required to operate in very different frequency ranges over a wide frequency band.
STMicroelectronics Application Notes AN2321, “Reference design: high performance, L6599-based HB-LLC adapter with PFC for laptop computers”, August 2006 and AN2393, “Reference design: wide range 200 W L6599-based HB LLC resonant converter for LCD TV & flat panels”, September 2006 disclose cascaded PFC and half bridge LLC power converters each using an L6563 controller for the PFC converter (in transition mode in AN2321, using FOT control in AN2393) and a separate L6599 resonant controller for the LLC converter. Reference is also directed in these respects to STMicroelectronics data sheets L6563, “Advanced transition-mode PFC controller”, November 2006 and L6599, “High-voltage resonant controller”, July 2006.
It is desirable to use an indirect control method as discussed above for the PFC control unit, to determine an off-time duty cycle for the PFC converter. As described in the document by Ben-Yaakov et al. referred to above, this control method typically involves multiplying an averaged converter input current by an output error voltage, and modulating the result to produce a PWM signal constituting an off-time duty cycle signal Doff. Such a control method presents a number of difficulties, especially for implementation in an IC operating at a typically low supply voltage.
In particular, with such control it is desirable to provide a relatively large gain for a voltage representing the sensed input current for a light converter load, but the gain is limited by the low supply voltage for sensed input current for heavier converter loads. Consequently, gain stages before and after a multiplier may typically be required. Providing a multiplier presents difficulties in terms of accuracy and the IC area that is required. In addition, it is convenient to represent the sensed converter input current with a negative voltage, which then needs to be handled by the multiplier. Lower amplitude signals have greater sensitivity to noise.
In addition, typically the PWM signal is produced by comparing the multiplier output signal with a ramp or sawtooth signal, which typically has a voltage from zero to a maximum ramp amplitude. In a CMOS IC, it may be difficult to provide an output swing of an amplifier to zero, so that the duty cycle range produced by comparing the output of a CMOS amplifier with a ramp signal may be restricted and/or non-linear.
A large dynamic range of an output voltage error amplifier of a PFC converter control unit is desirable because the PFC converter may typically be required to produce the same output voltage of about 380-400V from a rectified input AC voltage of about 85 to 265V rms, or about 120 to 375V peak. The square of the maximum to minimum ratio of this input voltage range is about 10, so that if the PFC converter is to handle this input voltage range and load conditions from full load to, for example, half load without unacceptable distortion, then the error amplifier must have a large output range of about 20:1.